Recently, the demands of higher speed and lower power consumption for digital electronic circuits to be adopted in a broad field have increased. A circuit which can meet such demands to some degree has recently been realized by a BiCMOS integrated circuit in which bipolar technology and CMOS technology are combined.
Also, a further large reduction in power consumption has been realized by a low-voltage technology, and thus, a 3.3 V power supply could be used instead of a 5 V power supply.
For this reason, for example, the realization of a low voltage output driving circuit which can be applied to a mixed voltage system containing equipment having respective power supplies of 5 V and 3.3 V is required, and some low-voltage output driving circuits are suggested for this purpose.
FIG. 5 is a circuit diagram of a conventional low-voltage output driving circuit which adopts this low-voltage technology.
In FIG. 5, 1 is a logic device. V.sub.CC represents a 3.3 V power supply voltage, for instance. Q.sub.1 -Q.sub.3 are npn bipolar transistors. NT.sub.1 -NT.sub.3 are n channel MOS transistors (hereinafter, referred to as NMOS transistors). PT.sub.1 -PT.sub.3 are p channel MOS transistors (hereinafter, referred to as PMOS transistors). D.sub.1 is a diode.
Also, the diode D.sub.1 can be a Schottky diode, for instance.
The input signal S.sub.IN and the control signal C.sub.IN are input to the logic device 1. In the logic device 1, three output levels are controlled by the control signal C.sub.IN. When this low-voltage output driving circuit functions as an ordinary buffer, the input level of the signal S.sub.IN is output as is. When the outputs of the low-voltage output driving circuit functions are in three state modes, which includes a high impedance state, the first and second outputs are set to a low level, and the third output is set to a high level.
The base of the bipolar transistor Q.sub.1 is connected to the first output of the logic device 1, and the collector of the transistor Q.sub.1 is connected to the cathode of the diode D.sub.1 and the collector of the bipolar transistor Q.sub.2, and the emitter of the transistor Q.sub.1 is connected to the base of the bipolar transistor Q.sub.2. The anode of the diode D.sub.1 is connected to the power supply voltage V.sub.CC.
The emitter of the bipolar transistor Q.sub.2 is connected to the drain of the PMOS transistor PT.sub.3 and the NMOS transistor NT.sub.3 and to the collector of the bipolar transistor Q.sub.3. At the same time, the emitter of the transistor Q.sub.2 is connected to the output line of the output signal S.sub.OUT.
The drains and also the gates of the PMOS transistor PT.sub.1 and the NMOS transistor NT.sub.1 are connected together. At the same time, the source of the PMOS transistor PT.sub.1 is connected to the power supply voltage V.sub.CC, and the source of the NMOS transistor NT.sub.1 is grounded. Thus, the first CMOS invertor INV.sub.C1 is constituted.
The input to the first CMOS invertor INV.sub.C1, namely, the point of connection of the gates of the PMOS transistor PT.sub.1 and the NMOS transistor NT.sub.1 is connected to the second output of the logic device 1, and the output, namely, the point of connection of the drains of both transistors, is connected to the gate of the PMOS transistor PT.sub.3.
The drains and also the gates of the PMOS transistor PT.sub.2 and the NMOS transistor NT.sub.2 are connected together. At the same time, the source of the PMOS transistor PT.sub.2 is connected to the power supply voltage V.sub.CC, and the source of the NMOS transistor NT.sub.2 is grounded. Thus, the second CMOS invertor INV.sub.C2 is constituted.
The input of the second CMOS invertor INV.sub.C2, namely, the point of connection of the gates of the PMOS transistor PT.sub.2 and the NMOS transistor NT.sub.2 is connected to the third output of the logic device 1, and the output, namely, the point of connection of the drains of both transistors is connected to the base of the bipolar transistor Q.sub.3 and the gate of the NMOS transistor NT.sub.3.
Also, the base of the bipolar transistor Q.sub.3 and the source of the NMOS transistor NT.sub.3 are grounded.
In this constitution, when the input signal S.sub.IN is input at a high level, since the bipolar transistor Q.sub.1 turns ON, the bipolar transistor Q.sub.2 turns ON.
Also, the output of the first CMOS invertor INV.sub.C1 goes low, and is supplied to the gate of the PMOS transistor PT.sub.3 for active pull-up. Thus, the PMOS transistor PT.sub.3 turns ON.
The output of the second CMOS invertor goes low, and is provided to the base of the bipolar transistor Q.sub.3 and the gate of the NMOS transistor NT.sub.3. Thus, the bipolar transistor Q.sub.3 and the NMOS transistor NT.sub.3 are maintained at the ON state.
The emitter voltage of the bipolar transistor Q.sub.2 is maintained two base-emitter voltage drops below the power supply voltage V.sub.CC because of the bipolar transistors Q.sub.1 and Q.sub.2. However, since the emitter of the bipolar transistor Q.sub.2 is connected to the drain of the p-channel MOS transistor PT.sub.3, the output signal S.sub.OUT is maintained to almost the power supply voltage V.sub.CC level, and is output.
On the other hand, when the input signal S.sub.IN is input at a low level, the bipolar transistors Q.sub.1 and Q.sub.2 are kept in the OFF state, the output of the first CMOS invertor INV.sub.C1 goes high, and the PMOS transistor PT.sub.3 is kept in the OFF state.
The output of the second CMOS invertor INV.sub.C2 goes high, and is supplied to the base of the bipolar transistor Q.sub.3 and the gate of the NMOS transistor NT.sub.3. Thus, the bipolar transistor Q.sub.3 and the NMOS transistor NT.sub.3 are maintained in the ON state.
As both the transistor Q.sub.3 and the NT.sub.3 are ON, the output signal S.sub.OUT is maintained at a ground level, and is output.
Also, at a time of three state logic, the first and second outputs of the logic device 1 are set to a low level, and are supplied to the base of the bipolar transistor Q.sub.1 and the input of the first CMOS invertor INV.sub.C1.
Thus, the bipolar transistors Q.sub.1 and Q.sub.2 are maintained in the OFF state, and since the output of the first CMOS invertor INV.sub.C1 goes high and is supplied to the gate of the PMOS transistor PT.sub.3, the PMOS transistor PT.sub.3 is also maintained in the OFF state.
On the other hand, the third output of the logic device 1 is set to a high level and is supplied to the input of the second CMOS invertor INV.sub.C2.
Thus, the output of the second CMOS invertor INV.sub.C2 goes low, and since it is supplied to the base of the bipolar transistor Q.sub.3 and the gate of the NMOS transistor NT.sub.3, the bipolar transistor Q.sub.3 and the NMOS transistor NT.sub.3 are maintained in the OFF state.
Therefore, the output line of the signal S.sub.OUT is maintained at the high impedance state.
As mentioned previously, since the circuit of FIG. 5 has the PMOS transistor PT.sub.3 for active pull-up, the level is too low at the time of high output, and cannot be regarded as a true high level at all. Also, the output corresponding to three states can be stably obtained.
However, in the above-mentioned conventional circuit, the output potential exceeds the power supply voltage V.sub.CC (3.3 V) by a composite voltage signal to be connected. For example, when it is 5 V, regardless of whether the gate level of the PMOS transistor PT.sub.3 for active pull-up is high (V.sub.CC) or low, the PMOS transistor PT.sub.3 is ON, and current flows from the output side to the power supply via the PMOS transistor PT.sub.3. In other words, there is the problem of leakage current.
It is therefore an object of this invention to provide a low-voltage output driving circuit capable of preventing the occurrence of leakage current.